EP1M120F484C8ES provides a speed-optimized PLD design, high-speed differential transceivers, and CDR support. These transceivers feature support for the LVDS, LVPECL, and 3.3-V PCML I/O standards and are implemented using the dedicated serializer, deserializer, and clock recovery circuitry in the HSDI. EP1M120F484C8ES may meet high-speed interface needs because to this circuitry, improved I/O elements (IOEs), and support for several I/O standards. The first PLDs with core performance optimization are Mercury devices. To reach peak performance, these LUT-based, improved memory devices make advantage of a network of quick routing resources. These tools are perfect for designs requiring a lot of data paths, registers, math, digital signal processing (DSP), or communications.
| Specification | Value |
|---|---|
| Number of LABs/CLBs | 480 |
| Number of Logic Elements/Cells | 4800 |
| Total RAM Bits | 49152 |
| Number of I/O | 303 |
| Number of Gates | 120000 |
| Voltage - Supply | 1.71V ~ 1.89V |
| Mounting Type | Surface Mount |
| Operating Temperature | 0℃ ~ 85℃ (TJ) |
| Package / Case | 484-BBGA, FCBGA |
| Supplier Device Package | 484-FBGA (23x23) |
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