Mercury devices provide a speed-optimized PLD design, high-speed differential transceivers, and CDR support. These transceivers feature support for the LVDS, LVPECL, and 3.3-V PCML I/O standards and are implemented using the dedicated serializer, deserializer, and clock recovery circuitry in the HSDI. Mercury devices may meet high-speed interface needs because to this circuitry, improved I/O elements (IOEs), and support for several I/O standards. The first PLDs with core performance optimization are Mercury devices. To reach peak performance, these LUT-based, improved memory devices make advantage of a network of quick routing resources. These tools are perfect for designs requiring a lot of data paths, registers, math, digital signal processing (DSP), or communications.
