EP1M120F484I7N provides a speed-optimized PLD design, high-speed differential transceivers, and CDR support. These transceivers feature support for the LVDS, LVPECL, and 3.3-V PCML I/O standards and are implemented using the dedicated serializer, deserializer, and clock recovery circuitry in the HSDI. EP1M120F484I7N may meet high-speed interface needs because to this circuitry, improved I/O elements (IOEs), and support for several I/O standards. The first PLDs with core performance optimization are Mercury devices. To reach peak performance, these LUT-based, improved memory devices make advantage of a network of quick routing resources. These tools are perfect for designs requiring a lot of data paths, registers, math, digital signal processing (DSP), or communications.
| Specification | Value |
|---|---|
| Series | Mercury |
| Number of Logic Blocks | 480 |
| Number of I/Os | 303 |
| Operating Supply Voltage | 3.3 V |
| Maximum Operating Temperature | + 85 C |
| Mounting Style | SMD/SMT |
| Package / Case | FBGA-484 |
| Distributed RAM | 49 kbit |
| Minimum Operating Temperature | - 40 C |
| Operating Supply Current | 30 mA |
| Packaging | Tray |
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