The logic array blocks (LABs) found in EPM3128ATI10010N device are made up of groups of 16 macrocells that range in size from 32 to 512. Each macrocell features a configurable register with separately programmable clock, clock enable, clear, and preset capabilities as well as a programmable AND/fixed-OR array. Each macrocell can be enhanced with up to 32 product terms, including shared expander and high-speed parallel expander product terms, in order to construct sophisticated logic functions.
The speed-critical parts of a design can operate at high speed and full power while the non-speed-critical parts operate at low speed and low power. With the use of this speed/power optimization tool, the designer can set up one or more macrocells to run at 50% or less power while only adding a small temporal delay. Additionally, EPM3128ATI10010N has a setting that lowers the output buffers' slew rate, decreasing noise transients during non-speed-critical signal switching. EPM3128ATI10010N can be utilized in mixed-voltage systems because all input pins are 2.5-V, 3.3-V, and 5.0-V tolerant and all output drivers can be tuned for 2.5 V or 3.3 V.
| Specification | Value |
|---|---|
| Programmable Type | In System Programmable |
| Delay Time tpd(1) Max | 7.5ns |
| Voltage Supply - Internal | 3V ~ 3.6V |
| Number of Logic Elements/Blocks | 8 |
| Number of Macrocells | 128 |
| Number of Gates | 2500 |
| Number of I/O | 98 |
| Operating Temperature | 0??C ~ 70??C (TA) |
| Mounting Type | Surface Mount |
| Package / Case | 256-BGA |
| Supplier Device Package | 256-FBGA (17x17) |
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