The logic array blocks (LABs) found in EPM3512AEQC208 device are made up of groups of 16 macrocells that range in size from 32 to 512. Each macrocell features a configurable register with separately programmable clock, clock enable, clear, and preset capabilities as well as a programmable AND/fixed-OR array. Each macrocell can be enhanced with up to 32 product terms, including shared expander and high-speed parallel expander product terms, in order to construct sophisticated logic functions.
The speed-critical parts of a design can operate at high speed and full power while the non-speed-critical parts operate at low speed and low power. With the use of this speed/power optimization tool, the designer can set up one or more macrocells to run at 50% or less power while only adding a small temporal delay. Additionally, EPM3512AEQC208 has a setting that lowers the output buffers' slew rate, decreasing noise transients during non-speed-critical signal switching. EPM3512AEQC208 can be utilized in mixed-voltage systems because all input pins are 2.5-V, 3.3-V, and 5.0-V tolerant and all output drivers can be tuned for 2.5 V or 3.3 V.
| Specification | Value |
|---|---|
| Series | MAX 3000A |
| Memory Type | EEPROM |
| Number of Macrocells | 512 |
| Maximum Operating Frequency | 116.3 MHz |
| Delay Time | 7.5 ns |
| Number of Programmable I/Os | 208 |
| Operating Supply Voltage | 3.3 V |
| Maximum Operating Temperature | + 70 C |
| Minimum Operating Temperature | 0 C |
| Package / Case | FBGA-256 |
| Mounting Style | SMD/SMT |
| Packaging | Tray |
| Supply Voltage - Max | 3.6 V |
| Supply Voltage - Min | 3 V |
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