High-density, high-performance PLDs in EPM7064LC68-15YY is based on Altera's second-generation MAX architecture and it is constructed using cutting-edge CMOS technology and offers counter speeds of up to 175.4 MHz, ISP, pin-to-pin delays as little as 5 ns, and 600 to 5,000 useable gates. The PCI Special Interest is met by MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in the -5, -6, -7, -10P, and -12P speed grades.
EPM7064LC68-15YY includes a number of improved features, including more global clocking, additional output enable controls, improved interconnect resources, fast input registers, and a programmable slew rate. The MAX 7000S devices, also known as the EPM7032S, EPM7064S, EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices, are in-system programmable MAX 7000 components. In addition to JTAG BST circuitry in devices with 128 or more macrocells, ISP, and an open-drain output option, MAX 7000S devices have the improved features of MAX 7000E devices.
| Specification | Value |
|---|---|
| Programmable Type | EE PLD |
| Delay Time tpd(1) Max | 15.0ns |
| Voltage Supply - Internal | 4.75V ~ 5.25V |
| Number of Logic Elements/Blocks | 4 |
| Number of Macrocells | 64 |
| Number of Gates | 1250 |
| Number of I/O | 52 |
| Operating Temperature | 0℃ ~ 70℃ (TA) |
| Mounting Type | Surface Mount |
| Supplier Device Package | 68-PLCC (24x24) |
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