EPM7256SRI208-10

EPM7256SRI208-10 Overview

The logic array blocks (LABs) in EPM7256SRI208-10, which are composed of groups of 16 macrocells, range in size from 32 to 256 macrocells. Each macrocell features a configurable register with separately programmable clock, clock enable, clear, and preset capabilities as well as a programmable AND/fixed-OR array. Each macrocell can be augmented with up to 32 product terms to form complicated logic functions, including shared expander product terms and high-speed parallel expander product terms.

Programmable speed/power optimization is offered by EPM7256SRI208-10. The speed-critical parts of a design can operate at high speed and full power while the non-speed-critical parts operate at low speed and low power. With the use of this speed/power optimization tool, the designer can set up one or more macrocells to run at 50% or less power while only adding a small temporal delay. Additionally, the EPM7256SRI208-10 offers a setting that lowers the output buffers' slew rate to lessen noise transients during non-speed-critical signal switching. All MAX 7000 devices, with the exception of 44-pin devices, include output drivers that can be configured for either 3.3-V or 5.0-V operation, enabling the use of MAX 7000 devices in mixed-voltage systems.

The Altera development systems are integrated programs that provide schematic, text—including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)—and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. These packages also support the EPM7256SRI208-10. For enhanced design entry and simulation support from other industry-standard PC- and UNIX-workstation based EDA tools, the software offers EDIF 2 0 0 and 3 0 0, LPM, VHDL, and Verilog HDL interfaces. The software is compatible with Windows-based computers, Sun SPARCstations, and workstations from the HP 9000 Series 700/800.

EPM7256SRI208-10 Features

• High-performance, MAX® 2nd generation-based EEPROM-based programmable logic devices (PLDs).

• 5.0-V in-system programmability (ISP) is possible with MAX 7000S devices thanks to their included IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface.

• ISP equipment that complies with IEEE Std. 1532.

• both 5.0-V ISP-based MAX 7000S devices and 5.0-V MAX 7000 devices are included.

• MAX7000S devices with 128 or more macrocells come with built-in JTAG boundary-scan test (BST) hardware.

• Logic densities for the whole EPLD family range from 600 to 5,000 useable gates (see Tables 1 and 2).

• pin-to-pin logic delays of 5 ns at counter frequencies of up to 175.4 MHz (interconnect included).

• There are devices that comply with PCI.

EPM7256SRI208-10 Applications

• Medical diagnostics and imaging

• Industrial motor control

• Industrial networking

• Machine vision

• IP and Smart camera

• Video and night vision equipment

• LTE radio and baseband

• Multifunction printers

EPM7256SRI208-10 Specifications