ISPGDX160VA5Q208-7

ISPGDX160VA5Q208-7 Overview

It exists in every I/O cell. Each output features two multiplexer control inputs (MUX0 and MUX1), two output latch clocks (CLK, CLKEN), and separate, programmable /O tri-state control (OE) inputs. Each I/0 cell has the ability to program the polarity of these signals. Up to four signal sources can be dynamically chosen for a specific output under the direction of a quick 4:1 MUX by the MUX0 and MUX1 inputs. With the MUX expander feature of each I/O and an increase in propagation latency of 2.0ns, a larger 16:1 MUX can be built. Selected sets of I/O pins can be used to directly drive the OE, CLK, CL KEN, MUX0, and MUX1 inputs. Clock-to-output delays are kept to a minimum by optional dedicated clock input pins. The same set of I/O pins are shared by CLK and CLKEN. When CLKEN=0, the register clock is turned off. It is possible to define links between I/O pins and architectural elements (such as output enable control, registered or locked inputs or outputs, etc.) through in-system programming. The ISPGDX160VA5Q208-7 don't have any programmable logic arrays due to their data path application focus. Schmitt trigger buffers for noise immunity are present on all input pins. The device's non-volatile E?CMOS technology is used to program these connections. With non-volatile technology, the device configuration is kept even when the power is turned off.

Additionally, there are no restrictions on pin-to-pin signal routing for 1:1 or 1:n. In other words, any 1/0 pin that is specified as an output can be driven by any l/0 pin that is defined as an input. Additionally, outputs can be adjusted to HIGH or LOW logic levels using the device pins (in jumper or DIP switch mode). Device outputs can be connected in parallel for increased drive and are designed for 24mA sink and 12mA source current (at JEDEC LVTTL levels). Each /o pin on the ISPGDX160VA5Q208-7 can be individually programmed for 3.3V or 2.5V output levels, as will be explained later. Each I/0 pin can have its own independently set program- mable output slew rate control to lower overall ground bouncing and switching noise. For improved testability, IEEE1149-1-compliant Boundary Scan Test circuitry is installed on AlI/0 pins. Additionally, through a unique set of private commands, the Test Access Port supports in-system programming. To endure "Iive inser-tion" system conditions, the ISPGDX160VA5Q208-7 1/Os was created. During the cycles of power-up and power-down, the /O buffers are disabled. Absolute maximum rating requirements for the Vco and I/O pins must still be met when designing for "live insertion."

ISPGDX160VA5Q208-7 Specifications