LCMXO3D-9400HC-5BG256C MachXO3D Family from Lattice Semiconductor

LCMXO3D-9400HC-5BG256C Overview

LCMXO3D-9400HC-5BG256C, which has improved security features and on-chip dual boot flash, is the next generation of Lattice Semiconductor Low Density PLDs. AES-128/256, Secure Hash Algorithm (SHA)-256, Elliptic Curve Digital Signature Algorithm (ECDSA), Elliptic Curve Integrated Encryption Scheme (ECIES), Hash Message Authentication Code (HMAC)-SHA256, Public Key Cryptography, and Unique Secure ID are some of the improved security features. LCMXO3D-9400HC-5BG256C is a Root-of-Trust hardware solution that, thanks to its improved bitstream security and user mode features, can easily expand to secure the entire system.

LCMXO3D-9400HC-5BG256C offers unprecedented I/O density and a large variety of I/O programmability choices. The device's I/O includes compatibility for the most recent industry standards, including as I3C and configurable slew rates. There are two low power, Flash-based PLDs in the LCMXO3D-9400HC-5BG256C that have densities of 4300 and 9400 Look-Up Tables (LUTs). On-chip dual boot configuration flash and multi-sectored User Flash Memory (UFM) are also features of MachXO3D devices. These devices include LUT-based programmable logic in addition to embedded block RAM (EBR), distributed RAM, locked loops (PLLs), pre-engineered source synchronous I/O support, advanced configuration support including on-chip dual-boot capability, and hardened variations of frequently used features like the SPI controller, the I2C controller, and the timer/counter.

LCMXO3D-9400HC-5BG256C is built using a non-volatile, low power 65-nm technology. The architecture of the device contains a number of characteristics, including programmable low swing differential I/O and the capacity to dynamically disable I/O banks, on-chip PLLs, and oscillators. These functions aid in controlling static and dynamic power consumption, resulting in minimal power usage for all family members.