LCMXO3L-640E-5MG121I

LCMXO3L-640E-5MG121I Overview

Description

The Ultra-Low Density LCMXO3L-640E-5MG121I enables the most cutting-edge programmable bridging and I/O extension. It has the lowest cost per I/O and the ground-breaking I/O density. The most recent industry standards for I/O are integrated support for the device's I/O functionality. Devices of the LCMXO3L-640E-5MG121I of low-power, instant-on, non-volatile PLDs have LUT densities ranging from 640 to 9400. Embedded Block RAM (EBR), Distributed RAM, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support, advanced configuration support, including dual-boot capability, and hardened versions of frequently used functions like SPI controller, I2C controller, and timer/counter are features of these devices in addition to LUT-based, low-cost programmable logic. User Flash Memory (UFM) is also supported by LCMXO3L-640E-5MG121I. These properties enable the use of these devices in consumer and system applications that are low-cost and high-volume. The LCMXO3L-640E-5MG121I is created using a non-volatile low-power technology with a 65nm pitch. The architecture of the device includes programmable low swing differential I/Os, as well as the ability to dynamically disable I/O banks, on-chip PLLs, and oscillators. All family members will experience low static power thanks to these capabilities that regulate static and dynamic power consumption. Two variants, C and E, with two-speed grades—-5 and -6, with -6 being the fastest—are offered for the LCMXO3L-640E-5MG121I. LCMXO3L-640E-5MG121I also offers User Flash Memory (UFM). These characteristics allow for the usage of these devices in low-cost, high-volume consumer and system applications. Using a non-volatile low-power technique with a 65nm pitch, the LCMXO3L-640E-5MG121I is made. The device's architecture enables dynamic disabling of oscillators, on-chip PLLs, and low swing differential I/Os in addition to programmable low swing differential I/Os. These skills to control static and dynamic power usage will result in low static power for the entire family. The LCMXO3L-640E-5MG121I is available in two types, C and E, with two-speed grades—-5 and -6, with -6 being the fastest. Controllable features include pull-up, pull-down, and bus-keeper on a "per-pin" basis. LCMXO3L-640E-5MG121I comes with an inbuilt oscillator that may be customized by the user. The timer/counter may divide the oscillator's clock output for use as the clock input in state machines that drive LEDs, scan keys, and other similar devices. The LCMXO3L-640E-5MG121I also offers on-chip NVCM/Flash configuration that is adaptable, dependable, and secure. These devices can also be set up by an external master using the JTAG test access port or the I2C port, or they can be set up by themselves using external SPI Flash. Pull-up, pull-down, and bus-keeper characteristics are all programmable on a "per-pin" basis. An oscillator incorporated into LCMXO3L-640E-5MG121I can be modified by the user. The oscillator's clock output may be divided by the timer/counter for use as the clock input in state machines driving LEDs, scanning keys, and other similar devices. The LCMXO3L-640E-5MG121I also provides an adjustable, dependable, and secure on-chip NVCM/Flash configuration. These devices can be configured by an external master using the I2C port or the JTAG test access port, or they can be configured independently using external SPI Flash. Lattice offers a wide range of pre-engineered IP (Intellectual Property) LatticeCORE modules that are tailored for theLCMXO3L-640E-5MG121I, including several reference designs that are freely licensed. Users are liberated to focus on the distinctive features of their designs, boosting productivity, by employing these adjustable soft core IP cores as standardized building blocks.

LCMXO3L-640E-5MG121I Specifications