Description
The Ultra-Low Density MachXO3 device family enables the most cutting-edge programmable bridging and I/O extension. It has the lowest cost per I/O and the ground-breaking I/O density. The most recent industry standards for I/O are integrated support for the device's I/O functionality. Five devices of the MachXO3L/LF family of low-power, instant-on, non-volatile PLDs have LUT densities ranging from 640 to 9400. Embedded Block RAM (EBR), Distributed RAM, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support, advanced configuration support, including dual-boot capability, and hardened versions of frequently used functions like SPI controller, I2C controller, and timer/counter are features of these devices in addition to LUT-based, low-cost programmable logic. User Flash Memory (UFM) is also supported by MachXO3LF devices. These properties enable the use of these devices in consumer and system applications that are low cost and high volume. The MachXO3L/LF devices are created using a non-volatile low power technology with a 65nm pitch. The architecture of the device includes programmable low swing differential I/Os, as well as the ability to dynamically disable I/O banks, on-chip PLLs, and oscillators. All family members will experience low static power thanks to these capabilities that regulate static and dynamic power consumption. Two variants, C and E, with two speed grades—-5 and -6, with -6 being the fastest—are offered for the MachXO3L/LF devices. MachXO3LF devices also offer User Flash Memory (UFM). These characteristics allow for the usage of these devices in low-cost, high-volume consumer and system applications. Using a non-volatile low power technique with a 65nm pitch, the MachXO3L/LF devices are made. The device's architecture enables dynamic disabling of oscillators, on-chip PLLs, and low swing differential I/Os in addition to programmable low swing differential I/Os. These skills to control static and dynamic power usage will result in low static power for the entire family. The MachXO3L/LF devices are available in two types, C and E, with two speed grades—-5 and -6, with -6 being the fastest. Controllable features include pull-up, pull-down, and bus-keeper on a "per-pin" basis. MachXO3L/LF devices come with an inbuilt oscillator that may be customized by the user. The timer/counter may divide the oscillator's clock output for use as the clock input in state machines that drive LEDs, scan keys, and other similar devices. The MachXO3L/LF devices also offer on-chip NVCM/Flash configuration that is adaptable, dependable, and secure. These devices can also be set up by an external master using the JTAG test access port or the I2C port, or they can be set up by themselves using external SPI Flash. Pull-up, pull-down, and bus-keeper characteristics are all programmable on a "per-pin" basis. An oscillator incorporated into MachXO3L/LF devices can be modified by the user. The oscillator's clock output may be divided by the timer/counter for use as the clock input in state machines driving LEDs, scanning keys, and other similar devices. The MachXO3L/LF devices also provide an adjustable, dependable, and secure on-chip NVCM/Flash configuration. These devices can be configured by an external master using the I2C port or the JTAG test access port, or they can be configured independently using external SPI Flash.Lattice offers a wide range of pre-engineered IP (Intellectual Property) LatticeCORE modules that are tailored for the MachXO3L/LF PLD family, including several reference designs that are freely licensed. Users are liberated to focus on the distinctive features of their designs, boosting productivity, by employing these adjustable soft core IP cores as standardized building blocks.
Features
1.1.1. Solutions
Smallest footprint, lowest power, high data throughput bridging solutions for mobile applications
Optimized footprint, logic density, I/O count, I/O performance devices for I/O management and logic applications
High I/O logic, lowest cost I/O, high I/O devices for I/O expansion applications
1.1.2. Flexible Architecture
Logic Density ranging from 64 to 9.4K LUT4
High I/O to LUT ratio with up to 384 I/O pins
1.1.3. Advanced Packaging
0.4 mm pitch: 1K to 4K densities in very small footprint WLCSP (2.5 mm × 2.5 mm to 3.8 mm ×3.8 mm) with 28 to 63 I/Os
0.5 mm pitch: 640 to 9.4K LUT densities in 6 mm x 6 mm to 10 mm x 10 mm BGA packages with up to 281 I/Os
0.8 mm pitch: 1K to 9.4K densities with up to 384 I/Os in BGA packages
1.1.4. Pre-Engineered Source Synchronous I/O
DDR registers in I/O cells
Dedicated gearing logic
7:1 Gearing for Display I/Os
Generic DDR, DDRx2, DDRx4
1.1.5. High Performance, Flexible I/O Buffer
Programmable sysI/O buffer supports wide range of interfaces:
LVCMOS 3.3/2.5/1.8/1.5/1.2
LVTTL
LVDS, Bus-LVDS, MLVDS, LVPECL
MIPI D-PHY Emulated
Schmitt trigger inputs, up to 0.5 V hysteresis
Ideal for I/O bridging applications
I/Os support hot socketing
On-chip differential termination
Programmable pull-up or pull-down mode
1.1.6. Flexible On-Chip Clocking
Eight primary clocks
Up to two edge clocks for high-speed I/O interfaces (top and bottom sides only)
Up to two analog PLLs per device with fractional-n frequency synthesis
Wide input frequency range (7 MHz to 400 MHz).
1.1.7. Non-volatile, Multi-time Programmable
Instant-on
Powers up in microseconds
Optional dual boot with external SPI memory
Single-chip, secure solution
Programmable through JTAG, SPI or I2C
MachXO3L includes multi-time programmable
NVCM
MachXO3LF reconfigurable Flash includes 100,000 write/erase cycle
Supports background programming of non volatile memory
1.1.8. TransFR Reconfiguration
In-field logic update while I/O holds the system state
1.1.9. Enhanced System Level Support
On-chip hardened functions: SPI, I2C, timer/counter
On-chip oscillator with 5.5% accuracy
Unique TraceID for system tracking
Single power supply with extended operating range
IEEE Standard 1149.1 boundary scan
IEEE 1532 compliant in-system programming
1.1.10. Applications
Consumer Electronics
Compute and Storage
Wireless Communications
Industrial Control Systems
Automotive System
1.1.11. Low Cost Migration Path
Migration from the Flash based MachXO3LF to the NVCM based MachXO3L
Pin compatible and equivalent timing
