LFE2-50E-L-EV

LFE2-50E-L-EV Overview

The LFE2-50E-L-EV of FPGA devices are designed to give high-performance capabilities including sophisticated DSP blocks, high-speed SERDES (LatticeECP2M family only), and high-speed source synchronous interfaces in a budget-friendly FPGA fabric. This combination was made possible by 90nm technology and improvements in device architecture. High performance and low cost are priorities when designing the LFE2-50E-L-EV fabric. The LFE2-50E-L-EV feature encryption ("S" versions only) and dual boot capabilities, as well as LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), Delay Locked Loops (DLLs), pre-engineered source synchronous I/O support, and enhanced sysDSP blocks. High-speed SERDES with PCS is a feature of the LFE2-50E-L-EV. These SERDES with PCS blocks, which have high jitter tolerance and low transmission jitter, can be set up to handle a variety of well-liked data protocols, including PCI Express, Ethernet (1GbE and SGMII), OBSAI, and CPRI. Chip-to-chip and small form factor backplane applications are well suited for SERDES thanks to their transmit pre-emphasis and receive equalization settings. Large complicated designs can be efficiently built using the LFE2-50E-L-EV thanks to Lattice Diamond design software. Popular logic synthesis tools include support for LFE2-50E-L-EV synthesis libraries. The Diamond software places and routes the design in the LFE2-50E-L-EV using the output from the synthesis tool and the limitations of its floor planning tools. For timing verification, the Diamond design tool pulls the timing from the routing and back-annotates it into the design. For the LFE2-50E-L-EV, Lattice offers a wide variety of pre-engineered IP (Intellectual Property) modules. Because these IP cores serve as standardized building blocks, designers are free to focus on the distinctive features of their designs, which boosts productivity.

LFE2-50E-L-EV Specifications