M5LV-256/120-5YC-7

M5LV-256/120-5YC-7 Overview

A wide variety of high-density and high-I/O Complex Programmable Logic Devices (CPLDs) are included in the M5LV-256/120-5YC-7. Fast speeds at high CPLD densities, low power consumption, and support for extra features like in-system programmability, Boundary Scan testability, and advanced clocking choices are all provided by the fifth-generation MACH architecture. Both 5-V (M5-xxx) and 3.3-V (M5LV-xxx) operations are available from the M5LV-256/120-5YC-7. M5LV-256/120-5YC-7 is produced with pin-to-pin delays as quick as 5.5 ns using E2 CMOS process technologies in cutting-edge ISO 9000-certified fabrication facilities. The PCI Local Bus Specification is adhered to by devices having 5.5, 6.5, 7.5, 10, and 12-ns specifications.

FUNCTIONAL DESCRIPTION

M5LV-256/120-5YC-7 includes a wide range of high-density and high-I/O Complex Programmable Logic Devices (CPLDs). The fifth-generation MACH architecture offers quick speeds at high CPLD densities, low power consumption, and support for extra features including in-system programmability, Boundary Scan testability, and advanced clocking options. The M5LV-256/120-5YC-7 offers 3.3-V (M5LV-xxx) and 5-V (M5-xxx) operations. Modern ISO 9000-certified manufacturing facilities use the E2 CMOS technology to manufacture M5LV-256/120-5YC-7 with pin-to-pin delays as fast as 5.5 ns. Devices with 5.5, 6.5, 7.5, 10, and 12-ns specifications comply with the PCI Local Bus Specification.

M5LV-256/120-5YC-7 Specifications