The act of configuring involves loading a design from a bitstream file into the internal configuration memory of the FPGA. The act of reading configuration information from a programmed FPGA back into a file is known as readback. Configuration Modes, Bit Generation Options, and Configuration Process and Flow are the three primary divisions of this application note. All the various modes are displayed in the Configuration Modes Section along with descriptions, functional timing waveforms, and schematic diagrams. In addition to displaying the configuration frame format and content, the Bit Generation Options section of the ispLEVER Bitstream Data Generator software program outlines the options available when creating a Bitstream file. The states of operation of the device during configuration, various configuration options, configuration frame sizes, and bitstream file error responses are all described in the Configuration Process and Flow section. There are no device configuration performance timing numbers in this paper. For timing information, consult the ORCA Series 4 Data Sheet.
| Specification | Value |
|---|---|
| Number of Gates | 333 K to 643 K |
| Number of Logic Blocks | 1296 |
| Embedded Block RAM - EBR | 111 Kbit |
| Number of I/Os | 372 |
| Maximum Operating Frequency | 168 MHz |
| Operating Supply Voltage | 1.425 V to 1.575 V, 3 V to 3.6 V |
| Maximum Operating Temperature | + 125 C |
| Mounting Style | SMD/SMT |
| Package / Case | fpBGA-680 |
| Minimum Operating Temperature | - 40℃ |
| Factory Pack Quantity | 24 |
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