Large Xilinx FPGA configuration bitstreams can be stored using the simple, affordable XC1701JC device. Programmable configuration within the system PROMs from Xilinx are currently offered in the XC1701JC. The FPGA generates a configuration clock while it is in Master Serial mode, which is used to operate the PROM. After a brief access time following the activation of CE and OE, data is available on the PROM DATA (D0) pin, which is linked to the FPGA DIN pin. Fresh data becomes temporarily available after each rising clock edge. The FPGA generates the appropriate amount of clock pulses to complete the configuration. The PROM and the FPGA are clocked by an external clock while the FPGA is operating in slave serial mode.
The XC1701JC produces a configuration clock that drives the PROM when it is operating in Master SelectMAP mode. The configuration clock that powers the PROM and the FPGA is produced by an external oscillator when the FPGA is operating in Slave Parallel or Slave SelectMAP mode. Data is accessible on the PROM's DATA (D0-D7) pins once CE and OE have been enabled. After each rising clock edge, fresh data becomes accessible for a brief period of time. On the CCLK's subsequent rising edge, the data is clock into the FPGA. In the Slave Parallel or Slave SelecMAP modes, a free-running oscillator may be utilized. By driving the CE input of the next device with the CEO output, multiple devices can be cascaded. All the PROMs in this chain's clock inputs and DATA outputs are connected. XC1701JC device works with the others in the family as well as the XC17V00 one-time programmable serial PROM family and can be cascaded.
8-pin SOIC, 8-pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC, 44-pin PLCC, or 44-pin VQFP are available in small plastic containers.
Support for programming from top programmer manufacturers
Support for design utilizing the software suites Xilinx Alliance and FoundationTM
20-year life data retention that is guaranteed
Packaging without lead (Pb) is available
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