XC4005-6PCG84I offers the advantages of bespoke CMOS VLSI without the upfront costs, delays, or inherent risks of a traditional masked gate array. The Configurable Logic Blocks (CLBs) in XC4005-6PCG84I device offer a regular, adaptable, programmable architecture that is encircled by programmable Input/Output Blocks (IOBs) and connected by a strong hierarchy of adjustable routing resources. This device in the XC4000-family have ample routing capacity to support even the most intricate connectivity configurations.
Reduced sets of routing resources on XC4005-6PCG84I is adequate given its smaller size. The available I/O is approximately doubled in XC4000H high I/O devices while maintaining the same routing resources and CLB topology as the XC4000 family. By inserting configuration data into the internal memory cells, the devices are modified. The configuration data can be actively read out of an external serial or byteparallel PROM by the FPGA (master modes) or written into the FPGA (slave and peripheral modes).
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