XC73108-12PG144I XC7300 CMOS EPLD from Xilinx, Inc

XC73108-12PG144I Overview

The AMD Xilinx XC73108-12PG144I is an integrated circuit that falls under the category of Field Programmable Gate Arrays (FPGAs). All XC73108-12PG144I EPLDs include programmable power management features to specify high-performance or low-power operation on an individual Macrocell-by-Macrocell basis. Unused Macrocells are automatically turned off to minimize power dissipation. Designers can operate speed-critical paths at maximum performance, while non-critical paths dissipate less power. Xilinx development software supports XC73108-12PG144I EPLD design using third-party schematic entry tools, HDL compilers, or direct equation-based text files. Using a PC or a workstation and one of these design capture methods, designs are automatically mapped to this device in a matter of minutes. This device is available in plastic and ceramic leaded chip carriers, pin-grid-array (PGA), ball-grid-array (BGA), and quad flat pack (QFP) packages. Package options include both windowed ceramic for design prototypes and one-time programmable plastic versions for cost-effective production volume. View Substitutes & Alternatives, datasheets, stock, pricing from Vemeko, as well as other FPGAs goods, at www.vemeko.com.

XC73108-12PG144I Features

Block RAM with a built-in FIFO for on-chip data buffering, 36 Kb, twin ports.
High-speed SelectIOTM technology that is compatible with DDR3 connections of up to 1,866 Mb/s.
High-speed serial communication with integrated multi-gigabit transceivers, providing a dedicated low-power mode that is suited for chip-to-chip interfaces, with maximum speeds ranging from 600 Mb/s to 6.6 Gb/s up to 28.05 Gb/s.
A user-configurable analog interface (XADC) with dual 12-bit 1MSPS analog-to-digital converters with supply and heat sensors built right into the chip.
DSP slices with an optimized symmetric coefficient filter and a 25 x 18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering.
Phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks are combined in powerful clock management tiles (CMT) for high precision and low jitter.
Utilize the MicroBlazeTM processor to quickly install embedded processing.
PCI Express® (PCIe) integrated block supports up to x8 Gen3 Endpoint and Root Port designs.
Numerous configuration options, including HMAC/SHA-256 authentication, built-in SEU detection and correction, and support for common memory types.

XC73108-12PG144I Applications

Portable ultrasound
Industrial control
Sensor fusion
Vehicles and transportation
Embedded vision
Consumer electronics
Medical devices

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