XC73108-WC84ACK

XC73108-WC84ACK Overview

All XC73108-WC84ACK EPLDs include programmable power management features to specify high-performance or low-power operation on an individual Macrocell-by-Macrocell basis. Unused Macrocells are automatically turned off to minimize power dissipation. Designers can operate speed-critical paths at maximum performance, while non-critical paths dissipate less power. Xilinx development software supports XC73108-WC84ACK EPLD design using third-party schematic entry tools, HDL compilers, or direct equation-based text files. Using a PC or a workstation and one of these design capture methods, designs are automatically mapped to an XC73108-WC84ACK EPLD in a matter of minutes. The XC73108-WC84ACK devices are available in plastic and ceramic leaded chip carriers, pin-grid-array (PGA), ball-grid-array (BGA), and quad flat pack (QFP) packages. Package options include both windowed ceramic for design prototypes and one-time programmable plastic versions for cost-effective production volume.

XC73108-WC84ACK Features

• High-speed arithmetic carry network with 18-bit accumulators operating at 43 to 61 MHz and a 1 ns ripple-carry latency per bit 

• Several separate clocks 

• Every input can be set to be registered, latched, or direct. 

• 24 mA high-drive output with 3.3 V or 5 V I/O operation 

• 3.3 V ±0.3 V JEDEC Standard (8-1A) is met. 

• Options for power control 

• Several security components to safeguard designs 

• Equipped with design and verification tools that are industry standard 

• PCI compliance is 100%

XC73108-WC84ACK Applications

• Industrial control

• Sensor fusion

• Vehicles and transportation

• Embedded vision

• Consumer electronics

• Medical devices

• Defense applications

• The embedded OEM

XC73108-WC84ACK Specifications