XC73108TM-15CPC84ACK XC7300 CMOS EPLD from Xilinx, Inc

XC73108TM-15CPC84ACK Overview

All XC73108TM-15CPC84ACK EPLDs include programmable power management features to specify high-performance or low-power operation on an individual Macrocell-by-Macrocell basis. Unused Macrocells are automatically turned off to minimize power dissipation. Designers can operate speed-critical paths at maximum performance, while non-critical paths dissipate less power. Xilinx development software supports XC73108TM-15CPC84ACK EPLD design using third-party schematic entry tools, HDL compilers, or direct equation-based text files. Using a PC or a workstation and one of these design capture methods, designs are automatically mapped to an XC73108TM-15CPC84ACK EPLD in a matter of minutes. The XC73108TM-15CPC84ACK devices are available in plastic and ceramic leaded chip carriers, pin-grid-array (PGA), ball-grid-array (BGA), and quad flat pack (QFP) packages. Package options include both windowed ceramic for design prototypes and one-time programmable plastic versions for cost-effective production volume. View Substitutes & Alternatives, datasheets, stock, pricing from Authorized Distributors, as well as other FPGAs goods, at www.vemeko.com.

XC73108TM-15CPC84ACK Features

Fast function blocks and high-density function blocks comprise the advanced dual-block architecture (XC7354, XC7372, XC73108, XC73144).
Interconnect matrix at 100%
High-speed arithmetic carry network with 18-bit accumulators operating at 43 to 61 MHz and a 1 ns ripple-carry latency per bit
Several separate clocks
Every input can be set to be registered, latched, or direct.
24 mA high-drive output with 3.3 V or 5 V I/O operation
3.3 V ±0.3 V JEDEC Standard (8-1A) is met.
Options for power control
Several security components to safeguard designs