XC73108TM-15PC84C XC7300 CMOS EPLD from Xilinx, Inc

XC73108TM-15PC84C Overview

All XC73108TM-15PC84C EPLDs include programmable power management features to specify high-performance or low-power operation on an individual Macrocell-by-Macrocell basis. Unused Macrocells are automatically turned off to minimize power dissipation. Designers can operate speed-critical paths at maximum performance, while non-critical paths dissipate less power. Xilinx development software supports XC73108TM-15PC84C EPLD design using third-party schematic entry tools, HDL compilers, or direct equation-based text files. Using a PC or a workstation and one of these design capture methods, designs are automatically mapped to an XC73108TM-15PC84C EPLD in a matter of minutes. The XC73108TM-15PC84C devices are available in plastic and ceramic leaded chip carriers, pin-grid-array (PGA), ball-grid-array (BGA), and quad flat pack (QFP) packages. Package options include both windowed ceramic for design prototypes and one-time programmable plastic versions for cost-effective production volume. View Substitutes & Alternatives, datasheets, stock, pricing from Authorized Distributors, as well as other FPGAs goods, at www.vemeko.com.

XC73108TM-15PC84C Features

Real 6-input lookup table (LUT)-based advanced high-performance FPGA logic that may be configured as distributed memory.
Block RAM with a built-in FIFO for on-chip data buffering, 36 Kb, twin ports.
High-speed SelectIOTM technology that is compatible with DDR3 connections of up to 1,866 Mb/s.
High-speed serial communication with integrated multi-gigabit transceivers, providing a dedicated low-power mode that is suited for chip-to-chip interfaces, with maximum speeds ranging from 600 Mb/s to 6.6 Gb/s up to 28.05 Gb/s.
A user-configurable analog interface (XADC) with dual 12-bit 1MSPS analog-to-digital converters with supply and heat sensors built right into the chip.
DSP slices with an optimized symmetric coefficient filter and a 25 x 18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering.
Phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks are combined in powerful clock management tiles (CMT) for high precision and low jitter.