XC7372-10PC68ACK XC7300 CMOS EPLD from Xilinx, Inc

XC7372-10PC68ACK Overview

The XC7372-10PC68ACK comes in pin-grid array (PGA), ball-grid array (BGA), and quad flat pack (QFP) packaging, as well as plastic and ceramic leaded chip carriers. Windowed ceramic packaging for design prototypes and one-time programmable plastic packaging for high production volumes are available as alternatives. The XC7372-10PC68ACK Devices have a special Dual-Block design that allows for high density capability via High Density Function Blocks and/or high speed operations via Fast Function Blocks. For crucial decoding and ultrafast state machine applications, Fast Function Blocks (FFBs) offer fast, pin-to-pin speed and logic throughput. For adders, accumulators, wide functions, state machines needing a large number of product terms, and other types of complicated logic, High-Density Function Blocks (FBs) offer the maximum logic density and system-level functionality to construct complex functions with predictable time. The Universal Interconnect Matrix (UIM), which ensures 100% interconnectivity of all internal processes, is also utilized by the XC7372TMPC68 architecture. For any routing path across the UIM, this interconnect architecture offers consistent, brief connectivity delays. Constant connectivity delays, independent of logic arrangement within the chip, simplify device timing and ensure design performance. View Substitutes & Alternatives, datasheets, stock, pricing from Authorized Distributors, as well as other FPGAs goods, at www.vemeko.com.

XC7372-10PC68ACK Features

MicroBlaze™ processor: The MicroBlaze™ processor is a soft processor that can be used to quickly deploy embedded processing.
36 Kb dual-port block RAM: The 36 Kb dual-port block RAM has integrated FIFO circuitry for on-chip data buffering.
High-performance SelectIO™ technology: The high-performance SelectIO™ technology supports DDR3 interfaces up to 1,866 Mb/s.
Integrated PCI Express® (PCIe) block: The integrated PCI Express® (PCIe) block supports up to x8 Gen3 Endpoint and Root Port designs.
Powerful clock management tiles (CMT): The powerful clock management tiles (CMT) integrate mixed-mode clock manager (MMCM) and phase-locked loop (PLL) blocks for high precision and minimal jitter.
Dual 12-bit 1MSPS analog-to-digital converters: The dual 12-bit 1MSPS analog-to-digital converters with on-chip supply and heat sensors make up the user-configurable analog interface (XADC).