XC7372-12WC84I XC7300 CMOS EPLD from Xilinx, Inc

XC7372-12WC84I Overview

The XC7372-12WC84I comes in pin-grid array (PGA), ball-grid array (BGA), and quad flat pack (QFP) packaging, as well as plastic and ceramic leaded chip carriers. Windowed ceramic packaging for design prototypes and one-time programmable plastic packaging for high production volumes are available as alternatives. The XC7372-12WC84I Devices have a special Dual-Block design that allows for high density capability via High Density Function Blocks and/or high speed operations via Fast Function Blocks. For crucial decoding and ultrafast state machine applications, Fast Function Blocks (FFBs) offer fast, pin-to-pin speed and logic throughput. For adders, accumulators, wide functions, state machines needing a large number of product terms, and other types of complicated logic, High-Density Function Blocks (FBs) offer the maximum logic density and system-level functionality to construct complex functions with predictable time. The Universal Interconnect Matrix (UIM), which ensures 100% interconnectivity of all internal processes, is also utilized by the XC7372-12WC84I architecture. For any routing path across the UIM, this interconnect architecture offers consistent, brief connectivity delays. Constant connectivity delays, independent of logic arrangement within the chip, simplify device timing and ensure design performance. View Substitutes & Alternatives, datasheets, stock, pricing from Authorized Distributors, as well as other FPGAs goods, at www.vemeko.com.

XC7372-12WC84I Features

High-speed serial communication with integrated multi-gigabit transceivers, providing a dedicated low-power mode that is suited for chip-to-chip interfaces, with maximum speeds ranging from 600 Mb/s to 6.6 Gb/s up to 28.05 Gb/s.
A user-configurable analog interface (XADC) with dual 12-bit 1MSPS analog-to-digital converters with supply and heat sensors built right into the chip.
DSP slices with an optimized symmetric coefficient filter and a 25 x 18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering.
Phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks are combined in powerful clock management tiles (CMT) for high precision and low jitter.
Utilize the MicroBlazeTM processor to quickly install embedded processing.
PCI Express® (PCIe) integrated block supports up to x8 Gen3 Endpoint and Root Port designs.
Numerous configuration options, including HMAC/SHA-256 authentication, built-in SEU detection and correction, and support for common memory types.