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Home > Product > Xilinx, Inc > XC7300 CMOS EPLD
XC7372-15PQ100C

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XC7372-15PQ100C

Manufacturer:
Xilinx
Package/Case:
QFP
RoHS:
Lifecycle:
Stock Resource:
Factory Excess Stock / Franchised Distributor
Datasheet:
XC7372-15PQ100C
Product Categories:
XC7300 CMOS EPLD
Description:
CMOS EPLD, ERASABLE PROGRAMMABLE LOGIC DEVICE
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XC7372-15PQ100C Overview

The XC7372-15PQ100C comes in pin-grid array (PGA), ball-grid array (BGA), and quad flat pack (QFP) packaging, as well as plastic and ceramic leaded chip carriers. Windowed ceramic packaging for design prototypes and one-time programmable plastic packaging for high production volumes are available as alternatives. The XC7372-15PQ100C Devices have a special Dual-Block design that allows for high density capability via High Density Function Blocks and/or high speed operations via Fast Function Blocks. For crucial decoding and ultrafast state machine applications, Fast Function Blocks (FFBs) offer fast, pin-to-pin speed and logic throughput. For adders, accumulators, wide functions, state machines needing a large number of product terms, and other types of complicated logic, High-Density Function Blocks (FBs) offer the maximum logic density and system-level functionality to construct complex functions with predictable time. The Universal Interconnect Matrix (UIM), which ensures 100% interconnectivity of all internal processes, is also utilized by the XC7372-15PQ100C architecture. For any routing path across the UIM, this interconnect architecture offers consistent, brief connectivity delays. Constant connectivity delays, independent of logic arrangement within the chip, simplify device timing and ensure design performance. View Substitutes & Alternatives, datasheets, stock, pricing from Authorized Distributors, as well as other FPGAs goods, at www.vemeko.com.


XC7372-15PQ100C Features

  • Erasable Programmable Logic Devices (EPLDs) with high performance: 5 / 7.5 ns pin-to-pin speeds on all fast inputs; maximum clock frequency of 167 MHz 

  • Fast function blocks and high-density function blocks comprise the advanced dual-block architecture (XC7354, XC7372, XC73108, XC73144). 

  • Interconnect matrix at 100% 

  • High-speed arithmetic carry network with 18-bit accumulators operating at 43 to 61 MHz and a 1 ns ripple-carry latency per bit 

  • Several separate clocks 

  • Every input can be set to be registered, latched, or direct. 

  • 24 mA high-drive output with 3.3 V or 5 V I/O operation 

  • 3.3 V ±0.3 V JEDEC Standard (8-1A) is met. 


XC7372-15PQ100C Applications

  • Automated manufacturing

  • Portable ultrasound

  • Industrial control

  • Sensor fusion

  • Vehicles and transportation

  • Embedded vision

  • Consumer electronics

  • Medical devices

  • Defense applications


XC7372-15PQ100C Specifications

SpecificationValue
Typical 22V10 Equivalent8
Number of Macrocells72
Number of Function Blocks8
Number of Flip-Flops126
Number of Fast Inputs12
Number of Signal Pins84

Application Field

  • AI

    Artificial Intelligence

  • 5G Technology

    5G Technology

  • Cloud Computing

    Cloud Computing

  • Consumer Electronics

    Consumer Electronics

  • Wireless

    Wireless Technology

  • Industrial Control

    Industrial Control

  • Internet of Things

    Internet of Things

  • Medical Equipment

    Medical Equipment

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