XC7372TM-12 XC7300 CMOS EPLD from Xilinx, Inc

XC7372TM-12 Overview

The XC7372TM-12 Devices have a special Dual-Block design that allows for high density capability via High Density Function Blocks and/or high speed operations via Fast Function Blocks. For crucial decoding and ultrafast state machine applications, Fast Function Blocks (FFBs) offer fast, pin-to-pin speed and logic throughput. For adders, accumulators, wide functions, state machines needing a large number of product terms, and other types of complicated logic, High-Density Function Blocks (FBs) offer the maximum logic density and system-level functionality to construct complex functions with predictable time. The Universal Interconnect Matrix (UIM), which ensures 100% interconnectivity of all internal processes, is also utilized by the XC7372TM-12 architecture. For any routing path across the UIM, this interconnect architecture offers consistent, brief connectivity delays. Constant connectivity delays, independent of logic arrangement within the chip, simplify device timing and ensure design performance. View Substitutes & Alternatives, datasheets, stock, pricing from Authorized Distributors, as well as other FPGAs goods, at www.vemeko.com.

XC7372TM-12 Features

Erasable Programmable Logic Devices (EPLDs) with high performance: 5 / 7.5 ns pin-to-pin speeds on all fast inputs; maximum clock frequency of 167 MHz
Fast function blocks and high-density function blocks comprise the advanced dual-block architecture (XC7354, XC7372, XC73108, XC73144).
Interconnect matrix at 100%
High-speed arithmetic carry network with 18-bit accumulators operating at 43 to 61 MHz and a 1 ns ripple-carry latency per bit
Several separate clocks
Every input can be set to be registered, latched, or direct.
24 mA high-drive output with 3.3 V or 5 V I/O operation