XCF32PFS48C Memory - Configuration Proms for FPGAs from Xilinx, Inc

XCF32PFS48C

Manufacturer:: Xilinx

Package/Case:: BGA48

RoHS:

Lifecycle:: Active

Stock Resource:: Factory Excess Stock / Franchised Distributor

Datasheet:

Product Categories:: Memory - Configuration Proms for FPGA's

Description:: FPGA Configuration PROM Memory

XCF32PFS48C Overview

Programmable configuration within the system In XCF32PFS48C, PROMs from Xilinx are currently accessible. The FPGA generates a configuration clock when it is in Master Serial mode, which is used to drive the PROM. After a brief access time following the activation of CE and OE, data is accessible on the PROM DATA (D0) pin, which is coupled to the FPGA DIN pin. Fresh data becomes temporarily available after each rising clock edge. The FPGA generates the appropriate number of clock pulses to complete the configuration. The PROM and the FPGA are clocked by an external clock when the FPGA is operating in slave serial mode. When it is in the Master SelectMAP mode, the XCF32PFS48C generates a configuration clock that drives the PROM.

XCF32PFS48C Features

• On-chip boot ROM

• 256 KB on-chip RAM (OCM)

• Byte-parity support

• Multiprotocol dynamic memory controller

XCF32PFS48C Applications

• Automotive driver assistance

• Driver information

• Video and night vision equipment

• LTE radio and baseband

• Multifunction printers

XCF32PFS48C Specifications

Specification	Value
Programmable Type	In System Programmable
Memory Size	32Mb
Voltage - Supply	1.65V ~ 2V
Operating Temperature	-40℃ ~ 85℃
Package / Case	48-TFBGA, CSPBGA
Supplier Device Package	48-CSP (8x9)