XQ4013E-3HQ240N

XQ4013E-3HQ240N Overview

In-system programmable configuration PROMs from Xilinx are now available in XQ4013E-3HQ240N. The PROM is driven by a configuration clock that the FPGA creates when it is operating in Master Serial mode. Data is accessible on the PROM DATA (D0) pin, which is coupled to the FPGA DIN pin, after a brief access time after CE and OE are enabled. After each rising clock edge, fresh data becomes accessible for a brief period of time. The right number of clock pulses are produced by the FPGA to finish the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock. The XQ4013E-3HQ240N produces a configuration clock that drives the PROM when it is operating in Master SelectMAP mode. The configuration clock that powers the PROM and the FPGA is produced by an external oscillator when the FPGA is operating in Slave Parallel or Slave SelectMAP mode. Data is accessible on the PROM's DATA (D0-D7) pins once CE and OE have been enabled. After each rising clock edge, fresh data becomes accessible for a brief period of time. On the CCLK's subsequent rising edge, the data is clock into the FPGA. In the Slave Parallel or Slave SelecMAP modes, a free-running oscillator may be utilized. By driving the CE input of the next device with the CEO output, multiple devices can be cascaded. All the PROMs in this chain's clock inputs and DATA outputs are connected. XQ4013E-3HQ240N device works with the others in the family as well as the XC17V00 one-time programmable serial PROM family and can be cascaded.

XQ4013E-3HQ240N Features

• System featured Field-Programmable Gate Arrays

• Select-RAMTM memory: on-chip ultra-fast RAM with

• Synchronous write option

• Dual-port RAM option

• Abundant flip-flops

• Flexible function generators

• Dedicated high-speed carry logic

• Wide edge decoders on each edge

• Hierarchy of interconnect lines

• Internal 3-state bus capability

• Eight global low-skew clock or signal distribution networks

• System Performance beyond 60 MHz

• Flexible Array Architecture

• Low Power Segmented Routing Architecture

• Systems-Oriented Features

• IEEE 1149.1-compatible boundary scan logic support

• Individually programmable output slew rate

• Programmable input pull-up or pull-down resistors

• 12 mA sink current per XQ4000E/EX output

• Configured by Loading Binary File

• Unlimited reprogrammability

• Readback Capability

• Program verification

• Internal node observability

• Backward Compatible with XC4000 Devices

• Development System runs on most common computer platforms

• Interfaces to popular design environments

• Fully automatic mapping, placement and routing

• Interactive design editor for design optimization

XQ4013E-3HQ240N Applications

• Automotive driver assistance

• Driver information

• Infotainment

• Broadcast camera

• Medical diagnostics and imaging

• Industrial motor control, industrial networking, and machine vision

XQ4013E-3HQ240N Specifications