EP2S60T-1020 uses a novel logic topology to maximize performance and enable device densities up to 180,000 equivalent logic elements (LEs). It is based on a 1.2-V, 90-nm, all-layer copper SRAM process. allowing demanding, memory-intensive applications, this EP2S60T-1020 provides up to 9 Mbits of on-chip TriMatrix memory. It also have up to 96 DSP blocks with up to 384 (18-bit 18-bit) multipliers allowing effective implementation of high performance filters and other DSP operations. There are several high-speed external memory interfaces that are supported, including single data rate (SDR) SDRAM, quad data rate (QDR) II SRAM, RLDRAM II, and double data rate (DDR) and DDR2 SDRAM. EP2S60T-1020 supports various I/O standards along with support for 1-gigabit per second (Gbps) source synchronous signaling with DPA circuitry.
With an internal clock frequency of up to 550 MHz and up to 12 phase-locked loops (PLLs), EP2S60T-1020 component provide a comprehensive clock management solution. Additionally, Stratix II devices are the first FPGAs in the market to be able to decrypt a configuration bitstream that has been encrypted with the Advanced Encryption Standard (AES) technique to safeguard designs.
| Specification | Value |
|---|---|
| Series | Stratix II |
| Number of Logic Blocks | 3022 |
| Number of I/Os | 718 |
| Operating Supply Voltage | 1.2 V to 3.3 V |
| Maximum Operating Temperature | + 70 C |
| Mounting Style | SMD/SMT |
| Package / Case | FBGA-1020 |
| Distributed RAM | 2.5 Mbit |
| Minimum Operating Temperature | 0 C |
| Operating Supply Current | 0.5 A |
| Packaging | Tray |
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