The proprietary XPLA (eXtended Programmable Logic Array) architecture is used by the Xilinx FZP CPLDs. In order to provide high speed and flexible logic allocation, the XPLA architecture incorporates the best aspects of both PLA and PAL type structures. This results in a superior capacity to make design modifications with fixed pinouts. Each logic block's XPLA structure offers a quick 8 ns PAL path with five specific product terms for each output. An second PLA structure connects this PAL line, deploying a pool of 32 product terms to a completely programmable OR array that may assign the PLA product terms to any output in the logic block. This combination supports up to 37 product terms on an output and enables efficient logic allocation across the logic block. No matter how many PLA product terms are employed, logic is allocated from the PLA array to an output in only 2.5 ns, resulting in worst-case tPDs of only 10.5 ns from any pin to any other pin. Additionally, to increase design density, logic that is shared by numerous outputs can be put on a single PLA product term and shared by those outputs via the OR array.
Industry-standard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Synopsys, Synario, Viewlogic, and Synplicity) that use text (ABEL, VHDL, Verilog) and/or schematic entry are compatible with the XCR3032 CPLDs. Industry-standard simulators are used for functional and temporal simulation during design verification. HP, Sparc, and personal computer platforms are all supported for development. A tool created by Xilinx called XPLA Professional is used for device fitting; it may be found on the Xilinx website.
Using industry standard device programmers from suppliers like Data I/O, BP Microsystems, SMS, and others, the XCR3032 CPLD can be reprogrammed.
